A Hierarchical Sparse Matrix Storage Format for Vector Processors

We describe and evaluate a Hierarchical Sparse Matrix (HiSM) storage format designed to be a unified format for sparse matrix applications on vector processors. The advantages that the format offers are low storage requirements, a flexible structure for element manipulations and allowing for efficient operations. To take full advantage of the format we also propose a vector architecture extension that supports the HiSM format. We show that utilizing the HiSM format we can achieve 40% reduction of storage space when comparing to the Compressed Row Storage (CRS) and Jagged Diagonal (JD) storage methods. Utilizing the HiSM storage on a vector processor we can significantly increase the vector performance for Sparse Matrix Vector Multiplication (SMVM) by 5.3 times compared to CRS and 4.07 times compared to JD. Finally, to illustrate the flexibility of the format we compared the cost of an element insertion against the JD and CRS formats. We show that for an element insertion operation HiSM outperforms JD for average and large matrices although it has a slight disadvantage for small matrices and always outperforms CRS between 2 and 400 times.